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Final schedule: Click here to open.

Instructions for presenters (oral and poster): Click here to open.

FINAL PROGRAM

TUESDAY, 9 MAY 2017

08:00 Registration opens

08:30 Exhibition opens

08:30 - 9:30 SESSION 4: Measurements & Characterization

Chair: U. Arz

08:30 - 08:50

Characterization Techniques of a Terabit Backplane using New Figures of Merit (slides)

M. Resso

Keysight Technologies, Santa Rosa, CA, USA

08:50 - 09:10

Measurement Based VRM Modeling (slides)

S.M. Sandler (H. Barnes)

PICOTEST, Phoenix, AZ, USA

09:10 - 09:30

Effective Method to Characterize the Bandwidth of Unknown Receiver

J. Liao, C. Mason, and S. Christianson

Intel Corporation, Hillsboro, Oregon, USA

09:30 - 10:30 SESSION 5: Power Delivery Networks

Chair: G. Signorini

09:30 - 09:50

Mesh-Sensitivity based Decoupling Capacitor Sizing and Placement for Power Delivery Networks (student paper)

N. Ambasana, and D. Gope

Indian Institute of Science, Bangalore, India

09:50 - 10:10

Power delivery network impedance characterization for high speed I/O interfaces using PRBS transmissions

D.M. Garcia-Mora (1), J. Garcia-Huanaco (1), V.J. Zuniga-Marquez (1), C.J. Franco-Tinoco (1), F. Yahyaei-Moayyed (2), and Kyle S. Unger (2)

(1) Intel Guadalajara Design Center, Mexico, (2) Intel Corporation, AZ, USA

10:10 - 10:30

Thermal Aware IR drop using Mesh Conforming Electro-Thermal Co-Analysis

J. Sercu, and H. Barnes

Keysight Technologies, Belgium

10:30 - 11:00 Coffee break

11:00 - 12:20 SESSION 6: Macromodeling & MOR

Chair: M. Nakhla

11:00 - 11:20

Order Reduction of Volterra and Volterra-Laguerre Models

M. Telescu, and N. Tanguy

Université de Bretagne Occidentale (UBO), Brest, France

11:20 - 11:40

Rational multi-delay models for long interconnects (student paper)

M. Zyari (1), Y. Rolain (1), and F. Ferranti (2)

(1) Vrije Universiteit, Belgium, (2) IMT Atlantique, CNRS Lab-STICC, Brest, France

11:40 - 12:00

A Novel Parametric Macromodeling Technique for Electromagnetic Structures with Propagation Delays (student paper) (slides)

M. Sgueglia (1), A. Sorrentino (1), M. de Magistris (1), D. Spina (2), D. Deschrijver (2), and T. Dhaene (2)

(1) University Federico II, Naples, Italy, (2) Ghent University, Belgium

12:00 - 12:20

Simulation of Buck Converters via Numerical Inverse Laplace Transform (slides)

R. Trinchero, I.S. Stievano, and F.G. Canavero

Politecnico di Torino, Italy

12:30 - 14:00 Lunch break

14:00 - 15:20 SESSION 7: High-Speed Link Design and Modeling

Chair: M. Telescu

14:00 - 14:20

SI Analysis of DDR Bus during Read/Write operation transitions

N. Bhagwath (1), A. Muranyi (1), D. Smirnov (1), C. Ferry (1), A. Sato (2), M. Ono (2), S. Ikeda (2), Y. Sugaya (2), T. Fukuhara (2), and R. Wolff (3)

(1) Mentor Graphics, USA, (2) Socionext, Japan, (3) Micron, USA

14:20 - 14:40

Deep Dive into DDR3 Interface Jitter Contributors

S. SM, K. Scholz, T. Bandyopadhyay, S. Moharil, S. Sinha, R. DeMoor

Texas Instruments Inc., Dallas, TX, USA

14:40 - 15:00

Exploration of Differential Via Stub Effect Mitigation by Using PAM4 and PAM8 Line Coding (student paper)

K. Scharff (1), T. Reuschel (1), X. Duany (2), H.-D. Bruns (1), and C. Schuster (1)

(1) Hamburg University of Technology (TUHH), Germany, (2) IBM Research and Development, Germany

15:00 - 15:20

A 45-GHz Wireless Transmission for a Wireless Interconnect Network-on-Board

T. Le Gouguec, P.-M. Martin

Université de Bretagne Occidentale (UBO), Brest, France

15:30 - 16:00 Coffee break

16:00 - 17:30 Industry Forum and Panel Discussion

Chair: R. Achar and S. Grivet-Talocia

William J. Lambert

Intel, USA

Hubert Harrer (slides)

IBM, Germany

Yutaka Uematsu (slides)

Hitachi, Japan

Vijay Boddu (slides)

Intel, USA

17:30 Exhibition closes

18:30 Gala dinner